[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"$fZw6x-8DH1kuoiGut-9Ny7vQRCW-BQHjqE-OfyzRRd24":3},{"code":4,"msg":5,"data":6},200,"操作成功",{"id":7,"title":8,"content":9,"digest":10,"source":10,"coverPath":11,"thumbsCoverPath":12,"isTop":13,"isShow":14,"baseClick":13,"clickCount":15,"createTime":16,"typeId":17,"isNewest":18,"newsInfoTypeRespVo":19,"voiceUrl":22,"voiceSize":23,"taskId":24,"releaseTime":25,"titleEn":26,"contentEn":27,"voiceUrlEn":28,"taskIdEn":29,"voiceSizeEn":30},2044,"新工艺实现多层单晶硅电路垂直集成","\u003Cp>\u003Cspan style=\"font-size: 18px;\">2026 年 6 月《科技日报》刊发消息，美国伊利诺伊大学厄巴纳 - 香槟分校团队攻克三维芯片制造关键难题，研发低温下单晶硅多层垂直集成新工艺，相关成果刊发于《自然》，为摩尔定律延续开辟全新路径。\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"font-size: 18px;\">当前晶体管尺寸逼近物理极限，传统平面微缩技术发展遇阻，垂直三维集成成为芯片性能升级主流方向，但长期受高温工艺掣肘：优质单晶硅制备需近 1000℃高温，极易损毁下层电路金属布线，行业限定后续叠加工序温度不能超 400℃。过往科研改用多晶硅、碳纳米管等替代材料制作上层器件，但器件性能、稳定性远不及底层单晶硅，严重制约芯片整体性能提升。\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"font-size: 18px;\">该团队从材料与结构双维度实现技术革新：先从源晶圆制备厚度低于 10 纳米的超薄单晶硅纳米薄膜，依托卷对卷层压工艺，在 200℃低温环境中将柔性硅膜精准贴合至预制下层电路基板，超薄硅膜的形变优势有效消除层间界面缺陷；同时创新采用无结晶体管架构，省去传统工艺必需的高温掺杂工序，彻底规避高温破坏底层电路的痛点。\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"font-size: 18px;\">依托这套工艺，研究团队成功制备三层垂直堆叠电路，每层集成 625 枚晶体管，器件平均良率达 98%，晶体管输出电流对标高温工艺量产的标准硅器件，综合性能大幅领先各类替代材料方案。\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"font-size: 18px;\">该研究证实标准单晶硅可实现规模化、高性能单片三维芯片集成，打破业界技术桎梏。目前科研团队已启动工艺产业化落地工作，对接半导体代工厂开展量产验证，未来有望通过垂直堆叠提升芯片晶体管密度，助力 AI 算力、高端存储等领域芯片迭代升级。\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>【新闻来源】科学网   https:\u002F\u002Fnews.sciencenet.cn\u002Fhtmlnews\u002F2026\u002F6\u002F565816.shtm\u003C\u002Fp>\u003Cp>（本网转发此文章，旨在为读者提供更多的信息资讯，所涉内容不构成投资、消费建议。文章事实如有疑问，请与有关方核实，文章观点非本网观点，仅供读者参考。）\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>","","https:\u002F\u002Fimage.51xinwei.com\u002F2026\u002F06\u002F714e67ae6ce9417898cbec7148b7507e\u002F芯位视野.png","https:\u002F\u002Fimage.51xinwei.com\u002F2026\u002F06\u002Fthumbs\u002F714e67ae6ce9417898cbec7148b7507e\u002F芯位视野.png",0,1,14,"2026-06-04 10:32",2,false,{"id":17,"name":20,"enName":21},"芯位视野","Xinwei Vision","https:\u002F\u002Fxinwei-dev-test.oss-cn-shenzhen.aliyuncs.com\u002Fintelligent\u002Faudio%3A651c53bd-0164-49f3-abe7-73017864eb4e%3A0.wav?Expires=1780548334&OSSAccessKeyId=LTAI5tNvY2RkKjZw4LLWsrPK&Signature=zv2w%2FxJcBJsqQqP9gOsyF4kiwpA%3D",3653958,"651c53bd-0164-49f3-abe7-73017864eb4e","2026-06-04 10:30","New Process Achieves Vertical Integration of Multi-Layer Single-Crystal Silicon Circuits","\u003Cp>\u003Cspan style=\"font-size: 18px;\">In June 2026, Science and Technology Daily published news that a team from the University of Illinois Urbana-Champaign in the United States overcame a key challenge in three-dimensional chip manufacturing. They developed a new process for low-temperature vertical integration of multi-layer single-crystal silicon. The related findings were published in Nature, opening a new path for the continuation of Moore's Law.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"font-size: 18px;\">Currently, transistor sizes are approaching physical limits, and the development of traditional planar scaling technologies has encountered obstacles. Vertical three-dimensional integration has become the mainstream direction for chip performance upgrades. However, it has long been constrained by high-temperature processes: high-quality single-crystal silicon preparation requires temperatures near 1000°C, which easily damages the metal interconnects on lower-layer circuits. The industry limits subsequent stacking process temperatures to no more than 400°C. Previous research used alternative materials such as polysilicon and carbon nanotubes to fabricate upper-layer devices, but their performance and stability were far inferior to the underlying single-crystal silicon, severely restricting overall chip performance improvement.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"font-size: 18px;\">The team achieved technological innovation from both material and structural dimensions. First, they prepared ultra-thin single-crystal silicon nanomembranes with thicknesses below 10 nanometers from a source wafer. Utilizing a roll-to-roll lamination process, they precisely bonded the flexible silicon membrane to a pre-fabricated lower-layer circuit substrate in a low-temperature environment of 200°C. The deformation advantages of the ultra-thin silicon membrane effectively eliminated interlayer interface defects. Simultaneously, they innovatively adopted a junctionless transistor architecture, eliminating the high-temperature doping step required in traditional processes, completely avoiding the pain point of high temperatures damaging the underlying circuits.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"font-size: 18px;\">Relying on this process, the research team successfully fabricated a three-layer vertically stacked circuit. Each layer integrated 625 transistors, achieving an average device yield of 98%. The transistor output current was comparable to standard silicon devices mass-produced via high-temperature processes, and the overall performance significantly surpassed various alternative material solutions.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"font-size: 18px;\">This research confirms that standard single-crystal silicon can achieve scalable, high-performance monolithic 3D chip integration, breaking through industry technical bottlenecks. Currently, the research team has initiated work on industrializing the process, collaborating with semiconductor foundries for mass production validation. In the future, it is expected to enhance chip transistor density through vertical stacking, assisting in the iterative upgrade of chips for fields such as AI computing power and high-end storage.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>【News Source】Science Net   https:\u002F\u002Fnews.sciencenet.cn\u002Fhtmlnews\u002F2026\u002F6\u002F565816.shtm\u003C\u002Fp>\u003Cp>(This website reposts this article to provide readers with more information. The content does not constitute investment or consumption advice. If there are questions regarding the facts in the article, please verify with the relevant parties. The views expressed in the article are not the views of this website and are for reference only.)\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>","https:\u002F\u002Fxinwei-dev-test.oss-cn-shenzhen.aliyuncs.com\u002Fintelligent\u002Faudio%3Afad2f7a8-bb53-4e2c-af00-c1a2b3e3571b%3A0.wav?Expires=1780548334&OSSAccessKeyId=LTAI5tNvY2RkKjZw4LLWsrPK&Signature=c8R2%2BiYqfc4nIqSdL1IC4HAapRE%3D","fad2f7a8-bb53-4e2c-af00-c1a2b3e3571b",6018154]